In recent years, together with improvements in the performance of information processing equipment such as devices for communication trunking and servers, the signal transmission/reception data rates within those devices or between devices have also increased. As a reception circuit (RX) that realizes these kinds of high data rates, a system is used in which the phase of a sampling clock is made to follow input data, for example.
To be specific, in the case where a reception circuit receives a 32-Gbps signal for example, because it is difficult for a logic circuit such as a CPU or a DSP to directly process that 32-Gbps signal, signals obtained by conversion into 2-Gbps×16 parallel signals by the reception circuit are processed.
In addition, for example, digital filter circuits are used, and input data and the sampling timing of a sampling clock are optimally adjusted. As with a CPU or a DSP, it is also difficult for these digital filter circuits to operate at high speed due to being logic circuits, and processing is carried out after parallelization has been carried out.
Moreover, although there are also digital filter circuits that are high-speed in analog, when a very large continuous-time filter is implemented, because a large RC is used for example, it is common for processing to be carried out by means of digital signals.
Furthermore, for example, a reception circuit has also been proposed that generates a master clock by means of a clock generator such as a phase-locked loop (PLL), and distributes that master clock to a plurality of block circuits (for example, CDRs described hereafter) and causes the plurality of block circuits to operate in a parallel manner.
Incidentally, within circuits that distribute a clock to a plurality of block circuits and carry out parallel operation, circuits are conventionally known that adjust clock phases in the block circuits.
Although a reception circuit that distributes a master clock to a plurality of block circuits and causes the plurality of block circuits to operate in a parallel manner has been proposed as previously mentioned, for example, when the clock phases of the plurality of block circuits coincide, internal circuits in those block circuits operate at the same timing and a large current flows.
To be specific, in the case where a reception circuit receives a 32-Gbps signal and outputs signals obtained by conversion into 2-Gbps×16 parallel signals for example, the number of internal circuits that carry out parallel operations by means of a slow clock increases even in one block circuit.
Consequently, for example, in the case where all of the internal circuits in the plurality of block circuits operate at the same timing, a large current momentarily flows and causes power source noise (simultaneous switching noise) to occur. When this kind of noise occurs, for example, it is not possible for data to be correctly determined by the reception circuit, which leads to a rise in the bit error rate (BER).
The following are reference documents.
[Document 1] Japanese Laid-open Patent Publication No. 2000-201059 and
[Document 2] Japanese Patent No. 2901657.